1. Field of the Invention
The present invention relates to a method of fabricating a display device, and more specifically, to a method of fabricating a liquid crystal display (LCD) device.
2. Description of the Related Art
In general, an LCD device controls light transmittance of liquid crystal cells in accordance with video signals, thereby displaying images corresponding to the video signals on an LCD panel having the liquid crystal cells arranged in a matrix configuration. In the LCD device, a thin film transistor (TFT) is commonly used as a switching device for the liquid crystal cells. The thin film transistor includes a semiconductor layer made from amorphous silicon or polycrystalline silicon. The amorphous silicon TFT has an advantage because it has relatively good material uniformity and stable operational properties. However, an amorphous silicon TFT has a relatively slow response due to its low charge mobility. Thus, it is difficult to employ an amorphous silicon TFT as a high-resolution display panel that requires rapid response speeds or as a driving device for a gate driver and a data driver. Conversely, a polycrystalline silicon TFT has an advantage because it functions well in high resolution display panels and has peripheral driving circuits mounted on the display panel since the charge mobility of polycrystalline silicon is high.
FIG. 1 is a schematic plan view of a polycrystalline silicon LCD device according to the related art. In FIG. 1, an LCD device using a polycrystalline silicon TFT includes an image display part 96 having a pixel matrix, a data driver 92 for driving a data line 4 of the image display part 96, and a gate driver 94 for driving a gate line 2 of the image display part 96. The picture display part 96 displays images by arranging liquid crystal cells (LCs) in a matrix configuration. Each of the LCs includes a TFT that functions as a switching device connected to a crossing of the gate line 2 and the data line 4, and is made from polycrystalline silicon in which an N-type dopant is injected.
As shown in FIGS. 2 and 3, an N-type TFT 30 in the image display part 96 includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and a drain electrode 10 connected to a pixel electrode 22 via a pixel contact hole 20 passing through a passivation film 18. The gate electrode 6 is formed to overlap a channel area 14C of an active layer formed on a buffer film 16, with a gate insulating film 12 positioned between the gate electrode 6 and the channel area 14C. The source electrode 8 is formed to be insulated from the gate electrode 6 with an interlayer insulating film 26 therebetween, and contacts a source area 14S of the active layer to which n+ ions are injected, via a source contact hole 24S. The drain electrode 10 is formed to be insulated from the gate electrode 6 with the interlayer insulating film 26 therebetween, and contacts a drain area 14D of the active layer to which the n+ ions are injected, via a drain contact hole 24D. In addition, a lightly doped drain (LDD) area 14L to which n− ions are injected is formed between the channel area 14C and the drain area 14D on the active layer, thereby decreasing a relatively high OFF-current. Such an N-type TFT 30 responds to a scanning pulse supplied from the gate line 2 to allow a video signal, i.e., a pixel signal, supplied from the data line 4 to be charged in one of the LCs. Accordingly, the LC controls light transmittance in accordance with the pixel signal charged in the LC.
FIG. 2 is a plan view of a lower array substrate according to the related art. In FIG. 2, a storage capacitor 60 includes a lower storage electrode 50 having PH3 injected into the active layer, and an upper storage electrode 52 overlapping the lower storage electrode 50 with the gate insulating film 12 positioned therebetween. The storage capacitor 60 allows a pixel signal charged in the pixel electrode 22 to be stably maintained until a next pixel signal is charged.
In FIG. 1, the gate driver 94 sequentially drives the gate lines 2 by horizontal intervals for each frame in response to gate control signals. The gate driver 94 causes the TFTs 30 to sequentially be turned ON for each horizontal line, thereby connecting the data line 4 to the LC. The data driver 92 samples digital data signals to convert the sampled signals into analog data signals for each horizontal period, and supplies the analog data signal to the data lines 4. Accordingly, the LCs connected to the turned-ON TFTs 30 control light transmittance in response to the analog data signals from the data lines 4.
The gate driver 94 and the data driver 92, respectively, include a CMOS structure having a plurality of driving P-type TFTs 90 and a plurality of driving N-type TFTs 80, as shown in FIGS. 2 and 3. In the driving P-type TFT 90, boron impurities are injected into a source area 74S and a drain area 74D on the active layer. In the driving N-type TFT 80, phosphorus impurities or arsenic impurities are injected into a source area 44S and a drain area 44D on the active layer. Furthermore, the driving N-type TFT 80 has an LDD area in order to decrease a high OFF-current in comparison with the driving P-type TFT 90.
Each of the driving N-type TFT 80 and the driving P-type TFT 90 includes active layers 44 and 74 formed on an upper portion of a buffer film 16 formed on a lower substrate 1, gate electrodes 36 and 66 formed to overlap the active layer 44 and 74 with a gate insulating film 12 positioned therebetween, and source electrodes 38 and 68, and drain electrodes 40 and 70 which are formed to insulate from the gate electrodes 36 and 66, and are contacted with the active layers 44 and 74.
FIG. 4 is a flow chart of a method of fabricating a lower array substrate according to the related art, and FIGS. 5A to 51 are cross sectional views along III1–III1′ and III2–III2′ of FIG. 2 of the method of fabricating a lower array substrate of FIG. 4 according to the related art.
At step S11, an insulating material such as a silicon oxide SiO2 is deposited on the entire lower substrate 1, to form a buffer film 16 as shown in FIG. 5A. An amorphous silicon film is deposited on the lower substrate 1 with the buffer film 16 thereon. The amorphous silicon film is then crystallized by a laser, to thereby form a polycrystalline silicon film. The polycrystalline silicon film is patterned by photolithography process using a first mask and etching process, thereby forming an active pattern including an active layer 14 of a N-type TFT having a N-type TFT of the picture display part and a N-type TFT of the driver, an active layer 74 of a P-type TFT in the driver, and an active layer 54 of a storage capacitor.
At step S12, a photo-resist is deposited on the entire surface of the lower substrate 1 having the active pattern. The photo-resist is then patterned by a photolithography process using a second mask, to thereby form a photo-resist pattern. The photo-resist pattern serves to expose the active layer 54 of the storage capacitor and is formed to entirely cover the active layers 14 and 74 of the N-type TFT and the P-type TFT. PH3 ions are injected into the active layer 54 of the storage capacitor by using the photo-resist pattern as a mask, so that a lower electrode 50 is formed as shown in FIG. 5B.
At step S13, an insulating material, such as silicon oxide SiO2, is deposited on the entire lower substrate 1 having the lower storage electrode 50, thereby forming a gate insulating film 12, as shown in FIG. 5C. Then, a gate metal layer is deposited on the entire surface of the lower substrate 1 with the gate insulating film 12 thereon. The gate metal layer is then patterned by a photolithographic process using a third mask and an etching process, thereby forming a gate electrode 6 of the N-type TFT and a gate electrode 66 of the P-type TFT. For example, the gate metal layer may be made of an aluminum metal material, such as aluminum Al and aluminum/neodymium. Subsequently, the n− ions are injected into the active layer 14 of the N-type TFT and the active layer 74, respectively, by using the gate electrodes 6 and 66 as a mask. Thus, the active layers 14 and 74 overlapped with the gate electrode 6 of the N-type TFT and the gate electrode 66 of the P-type TFT become channel areas 14C and 74C, respectively, whereas, the active layers 14 and 74 not overlapped with the gate electrode 6 of the N-type TFT and the gate electrode 66 of the P-type TFT become LDD areas 14L and 74L, respectively.
At step S14, a photo-resist is deposited on the entire surface of the lower substrate 1. Then, the photo-resist is patterned by a photolithographic process using a fourth mask, thereby forming a photo-resist pattern. The photo-resist pattern serves to partially expose the active layer 14 of the N-type TFT and is formed to entirely cover an upper storage electrode 52 and the active layer 74 of P-type TFT. Subsequently, the n+ ions are injected into the active layer 14 of the N-type TFT by using the photo-resist pattern as a mask, so that a source area 14S and a drain area 14D of the active layer 14 are formed, as shown in FIG. 5D.
At step S15, a photo-resist is deposited on the entire surface of the lower substrate 1 having the active layer 14 in which the n+ ions are injected and then the photo-resist is patterned by a photolithography process using a fifth mask, thereby a photo-resist pattern is formed. The photo-resist pattern is formed so as to cover an area except for the active layer 74 of the P-type TFT. Then, p+ ions are injected into the active layer 74 of the P-type TFT by using the photo-resist pattern as a mask, so that a source area 74S and a drain area 74D of the active layer 74 of the P-type TFT are formed, as shown in FIG. 5E.
At step S16, an insulating material is deposited on the lower substrate 1 having the active layer 74 to which p+ ions are injected, so that an interlayer insulating film is formed, as shown FIG. 5F. Then, the photo-resist is patterned by a photolithographic process using a sixth mask and an etching process. Accordingly, a source contact hole 24S and a drain contact hole 24D exposing the source area 14S and the drain area 14D of the N-type TFT are formed, respectively, and a source contact hole 84S and a drain contact hole 84D exposing the source area 74S and the drain area 74D of the P-type TFT are formed, respectively.
At step S17, a data metal layer is deposited on the entire surface of the lower substrate 1 having the source contact holes 24S and 74S and the drain contact holes 24D and 74D, and then the data metal layer is patterned by a photolithographic process using a seventh mask and an etching process, so that a data pattern, including the source and the drain electrodes 8 and 10 of the N-type TFT, and the source and the drain electrode 68 and 70 of the P-type TFT are formed, as shown in FIG. 5G. The source electrodes 8 and 68 and the drain electrodes 10 and 70 are contacted with the source areas 14S and 74S and the drain area 14D and 74D of the active layer via the source contact holes 24S and 84S and the drain contact holes 24D and 84D, respectively.
At step S18, an insulating material is deposited on the entire surface of the lower substrate 1 having the data pattern, thereby forming a passivation film 18, as shown in FIG. 5H. The lower substrate 1 having the passivation film 18 is placed inside a chamber, and is subjected to a heat treatment process using hydrogen H2. Accordingly, the hydrogen H2 is diffused into the passivation film 18 by the heat treatment process. The diffused hydrogen H2 is bonded with a dangling bond which does not bond with atoms in the active layers 44 and 74.
At step S19, the passivation film 18 is patterned by a photolithographic process using an eighth mask and an etching process, so that a pixel contact hole 20 is formed to expose the drain electrode 10 of the N-type TFT in the picture display part. Subsequently, a transparent conductive material is deposited on the entire surface of the lower substrate 1 having the passivation film 18, and the transparent conductive material is patterned by a photolithographic process using a ninth mask and an etching process, thereby forming a pixel electrode 22, as shown in FIG. 51. Accordingly, the pixel electrode 22 is electrically connected to the drain electrode 10 of the N-type TFT in the picture display part.
According to the related art, the fabricating method of a polycrystalline silicon TFT employs a nine mask process. In addition, since each mask process includes a plurality of sub-processes, such as deposition, cleaning, photolithography, etching, photo-resist stripping, and inspection, the fabricating process is very complicated and increases fabrication costs.